1. Field of the Invention
This invention generally relates to semiconductor integrated device design and fabrication and, more particularly, to techniques for isolating active areas of integrated circuits.
2. Description of the Related Art
As semiconductor integrated circuit technology advances to Ultra Large Scale Integration (ULSI) technologies, the devices on wafers shrink to sub-micron dimensions and the circuit density increases to several million devices per chip. Since the devices are closer together, isolation of the devices from each other becomes more problematic and more difficult to achieve. As such, the manufacturability and reliability of these devices are of great importance to the semiconductor industry and have received increasing attention recently.
For a given chip size, an increase in the number of active circuit components requires that they be placed in close proximity to each other, thus forcing a corresponding reduction in the surface area of the circuit that can be occupied by electrical isolation structures. The trend for reducing the chip surface area consumed by electrical isolation structures, while maintaining the necessary electrical isolation of adjacent active components, has led to the development of several different isolation techniques.
The most common isolation fabrication technique is a process known as LOCOS (for LOCalized Oxidation of Silicon). In the LOCOS process, the substrate is oxidized to form an isolation structure over the selected regions. These oxidized regions; are known as field oxide regions and they are typically positioned so as to separate active areas on the wafer where devices, such as transistors, will subsequently be formed.
In the conventional LOCOS technique, the process typically begins with the growth of a thin pad oxide layer over the wafer surface. The function of this layer is to prevent transfer of stresses between the silicon substrate and the subsequently deposited layers. Following this, a layer of silicon nitride mask is deposited on top of the pad oxide layer and lithographically defined to retain the nitride over the active device regions of the wafer. The nitride layer is etched from the area between the active device areas where the field oxide (silicon dioxide) isolation structure is to be thermally grown.
Although the LOCOS process offers high reliability and proven high volume manufacturing compatibility, the effectiveness of this technique is limited by two important factors. One factor is active area loss due to lateral encroachment of the growing field oxide, often referred to as xe2x80x9cbird""s beakxe2x80x9d encroachment, and the other factor is the problem of the field oxide isolation region thinning during formation which occurs especially in the narrow fields during the field oxide growth stage.
These problems are illustrated in FIG. 1, which shows a cross-section of a portion of a silicon substrate 40 having field oxide isolation regions 50a and 50b formed between a plurality of nitride masking stacks 60. The masking stacks 60 are positioned over the active areas 70 of the wafer 40. The lateral oxide encroachment into the active area is denoted by the distance labeled xe2x80x9cWxe2x80x9d, and the field oxide thicknesses for the narrow and the wide regions are denoted as xe2x80x9ctnoxxe2x80x9d and xe2x80x9ctwoxxe2x80x9d in isolation structures 50a and 50b, respectively. The bir""s beak encroachment is the result of lateral diffusion of the oxidants at the edges of the nitride masking stack and this bird""s beak encroachment causes the oxide layer to grow under and lift the edges of the nitride masking stack
Although the length of the lateral encroachment depends upon a number of parameters, including the thickness of the pad oxide, nitride and isolation oxide layers, as well as the oxidation temperature and pressure, the encroachment is generally related to the balance between the stress on the wafer from the masking stack, which inhibits the encroachment, and the stress generated by the growth of the field oxide which encourages encroachment. Both of these stresses introduce an increased number of stress induced defects into the silicon substrate adjacent to the active area and thereby increasing the junction leakage current of devices formed in these areas and, as such, reducing the overall reliability of the device.
Another limitation of LOCOS isolation technologies for submicron structures is the phenomenon of the field oxide thinning effect. Typically, narrower field oxide isolation regions formed on the substrate are thinner than wider field oxide isolation regions. This is illustrated in FIG. 1 wherein the wider isolation region 50b on the right hand side is thicker than the narrower isolation region 50a on the left hand side (Toxn less than Toxw). This inconsistent thickness of the field oxide isolation regions may also be associated with the build up of stress in the silicon substrate which can reduce the oxidation rate and hence the final oxide thickness.
Furthermore, for a given masking stack thickness on a wafer, the stress generated during the field oxide growth is observed to be a function of the field width. In fact, it is believed that the stress created by the field oxide growing in narrower spacings is sufficient to reduce the diffusivity of the oxidant through the oxide thereby reducing the thickness of the isolation regions. As a result of the field oxide thinning effect, device isolation characteristics in narrow isolation regions can be substantially reduced which can result in unwanted conductivity between the devices formed in adjacent active areas.
This problem has led to techniques for reducing the stress during the growth of the field oxide. For example, it is known that the stress exerted by the growing field oxide can be controlled by varying the viscosity of the field oxide. In particular, reducing the viscosity of the growing field oxide allows oxide to flow better. Methods of reducing the viscosity of the field oxide include employing either a high temperature oxidation process or a high pressure oxidation process (HiPOX). In semiconductor technology, a high temperature oxidation process can be either wet or dry oxidation carried out at a temperature of approximately 1000xc2x0 C. High temperature oxidation generally reduces the thinning problem in narrow field oxidation regions. This is due to a decrease in field oxide viscosity, which results in an increased oxide flow and a decreased level of stress in the field oxide allowing greater oxide growth. Unfortunately, raising the growth temperature is not a reasonable solution to the bird""s beak problem as higher temperatures severely increase bird""s beak oxide encroachment under the nitride masking stack. Since both minimal isolation region thinning and lateral oxide encroachment are essential for a high quality and defect free isolation process, there is a need for a better process to provide required viscosity reduction.
In this respect, the HiPOx (for High Pressure Oxidation) process may comprise an improvement. In fact, the HiPOx process reduces the field oxide thinning effect and also reduces the length of bird""s beak since the oxidation can be performed at a lower temperature range and in a shorter time period under the high pressure. A HiPOx process is typically carried out at a temperature range of 900-1000xc2x0 C. and under a pressure range of 20-25 Atm. The oxidation process takes place in a high pressure furnace by using an O2 gas ambient (dry oxidation) or a steam of H2O (wet oxidation) as oxidants.
However, even though the HiPOx process provides some advantages over other field oxide growth techniques, problems with the process and the special high pressure equipment have limited its acceptance in the industry. In particular, there are significant safety problems associated with high pressure oxidation due to the high pressure gasses that are used during the process. To address these safety problems, and also to accomplish the process, expensive and large high pressure furnaces and related equipment must be used to perform the process.
As is apparent, there is a need in current semiconductor technology for improved methods of forming isolation regions to reduce lateral encroachment and thinning of the isolation structures, thereby permitting smaller isolation structures to be used. To this end, there is a need to reduce the viscosity of the oxide during the field oxidation isolation process, thereby reducing the stress during the oxidation processes. Further, there is a particular need for a technique for forming isolation regions whereby the viscosity is lowered without using special equipment and the thickness is to a highly degree, uniform.
The aforementioned needs are satisfied by the process of the present invention which comprises exposing regions of a semiconductor wafer to an isolation structure forming agent and a viscosity reducing agent. The isolation structure forming agent changes regions of the semiconductor wafer into isolation structures and the viscosity agent decreases the viscosity of the isolation structures during formation. As a result of the decrease in viscosity, lateral encroachment of the isolation structures into adjacent active areas is reduced. Additionally, the decrease in the viscosity is accompanied by a decrease in the internal stress in the isolation structure during formation which enhances diffusion of the isolation structure forming agent to the semiconductor substrate, thereby resulting in thicker isolation structures.
In the preferred embodiment, a semiconductor wafer is masked and then regions of the wafer are exposed. An oxidation step is then performed whereby the semiconductor wafer is oxidized to form the isolation structure. During at least some of the time that the oxidation step is performed, a doping agent that reduces the viscosity of the oxidized semiconductor agent is added to the oxidation step. In one particular implementation, a silicon wafer is oxidized in the presence of fluorine which results in a silicon oxide isolation structure that has a decreased viscosity during formation.
The decrease in viscosity results in a decrease in the forces that prompt volumetric expansion of the isolation structure. This inhibits volumetric expansion underneath masking stacks as the masking stacks exert a compressive force on the portion of the silicon substrate underneath the masking stack. Hence, there is less lateral encroachment, i.e., bird""s beak encroachment, of the silicon oxide isolation structure into the regions under the masking stacks that can comprise the locations of active areas of the wafers.
Further, the decrease in viscosity of the silicon oxide results in oxygen molecules more readily diffusing through the silicon oxide isolation structure under formation to the interface between the silicon substrate and the silicon oxide isolation structure. This results in thicker silicon oxide isolation structures and is particularly useful in applications requiring very narrow isolation structures.
These and other objects and advantages of the present invention will become more fully apparent from the following description taken in conjunction with the accompanying drawings.